1. Field of Invention
This invention relates to timing signal generators; and more particularly, to such generators which generate timing signals having a set period and a delay time, and which may be used in LSI testing apparatus for testing semiconductor circuits.
2. Description of the Prior Art
The evolution of semiconductor devices, such as large scale integrated circuits (referred to as "LSI"), has been accompanied by increased complexity of various functions and construction thereof. Testing such devices involves using a LSI testing apparatus.
The LSI testing apparatus is generally constructed so as to determine the quality of the LSI to be tested (hereinafter referred to as a DUT) by applying a test signal, having various patterns and produced by test signal generating means, to the DUT, and by comparing the data output from the DUT with to an expected pattern prepared in advance in response to the applied test signal. In the test signal generating means, an accurate repeatable timing signal having a high resolution is used to create the test signal.
FIG. 1 shows a conventional timing signal generator, which is disclosed, for example, in Japan Patent S62/23495 and U.S. Pat. No. 4,231,104, and which comprises a rate generator for generating a reference clock Tsyn and a timing or rate signal Tout. The circuit comprises a programmable counter 1 for counting the clock Tosc from a quartz oscillator OSC and for outputting a dividing clock Tc having a period of m times the clock period (wherein m is an integer) when its value reaches a predetermined count, a first programmable delay apparatus (labelled "delay line") 2a for generating a timing signal having a period different from the m times the period of the clock Tosc by inputting clock Tc from programmable counter 1 and giving a delay period to the input dividing clock by repeatedly changing the delay time, and a second programmable delay apparatus (also labelled "delay line") 2b which gives the same amount of delay period as first delay apparatus 2a to the clock Tosc from oscillator OSC.
The delay times of delay apparatus 2a,2b are controlled by data stored in register 3. The data stored in register 3 is provided by adder 4. Adder 4 adds delay time data stored in a memory 5 to data stored in register 3 and loads data of the sum to the register 3 with respect to timing signal Tout from delay apparatus 2a. Accordingly, data stored in register 3 is updated each time timing signal Tout is outputted.
FIGS. 2a, 2b and 2c show the case when a timing signal Tout having a period of 50 ns(nano-seconds) is generated by using the circuit of FIG. 1.
Assume that data 2, as a delay change number, is stored initially in memory 5, and data 3, as a preset value of counter 1, is stored in memory 6. Also, assume that 0 is stored initially in register 3, and the delay time or period introduced by delay apparatus 2a, 2b is zero.
FIG. 2a shows clock Tosc, having a period of 16 ns, provided to counter 1. Counter 1 is provided with a preset value 3 read out from memory 6, and counts downward from preset value 3 for each count of clock Tosc shown in FIG. 2a and outputs a dividing clock Tc at the third clock pulse (i.e. after 16 ns.times.3=48 ns) as shown in FIG. 2b. This dividing clock Tc is applied directly to first programmable delay apparatus 2a.
Adder 4 adds data 3, as the delay change number stored in memory 5, to delay change data 0 in the register 3 and stores added value 2 in register 3 with respect to the first timing signal Tout. Accordingly, a clock Tc applied next to first delay apparatus 2a is delayed by 2 ns, as shown in FIG. 2c, based on delay time number 2 stored in register 3 and is outputted as a timing signal Tout 1. This timing signal appears after 50 ns (i.e. 16 ns.times.3+2 ns), that is, after the first timing signal was outputted.
Adder 4 adds data 2 as the delay change number stored in memory 5 to delay change number data 2 stored in register 3 and stores the added value 4 in register 3 with respect to the timing signal Tout 1. Accordingly, a clock Tc, applied to first delay apparatus 2a, is delayed by 4 ns, as shown in FIG. 2c, based on the delay time number 4 stored in register 3 and is outputted as a timing signal Tout 2. Timing signal Tout 2 appears 50 ns after timing signal Tout 1.
Thus, timing signal Tout, having a period which is different from m times the period of clock Tosc, is obtained from first delay apparatus 2a by appropriately selecting the preset value stored in memory 6 and delay change number data stored in memory 5.
Reference clock Tsyn, which is synchronous with the timing signal Tout, may be also obtained in a similar manner.
The conventional timing signal generator just described, however, has various problems. For example, because the reference clock Tsyn is provided by delaying the clock from oscillator OSC using the second programmable delay apparatus 2b, a discontinuity in phase occurs in reference clock Tsyn at the time where the signal from the programmable counter is delayed, thereby degrading timing accuracy. Furthermore, because the conventional device supplies the dividing pulse from counter 1 to the first delay apparatus 2a to cause its delay, the leading edge of the dividing pulse is attenuated between the transmission lines, and hence, produces inaccuracies. Also, disadvantageously, the conventional device requires a large number of expensive programmable delay apparatus.
Such programmable delay apparatus has various problems. For example, the production of such apparatus requires a long trace on a printed circuit and requires a considerable area on the printed circuit board to form taps therefor.
Moreover, the conventional generator is disadvantageous in that a large number of programmable delay lines is used, and such large number of delay lines requires use of a circuit for correcting the delay times to maintain an accurate delay time. This increases the possibilities of error because drift is brought about even after correction is provided.